Selected Papers Paper/Slide Download 
Hiroshi Sasaki, Satoshi Imamura, and Koji Inoue, "Coordinated Power-Performance Optimization in Manycores," In Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (PACT '13), pp.51-62, Sep. 2013. (acceptance rate: 36/208=17.3%)
 [Low-Power Cache]
Koji Inoue, Tohru Ishihara, and Kazuaki Murakami, "Way-Predicting Set-Associative Cache for High Performance and Low Energy Consumption,'' Proc. of 1999 International Symposium on Low Power Electronics and Design (ISLPED'99), pp.273-275, Aug. 1999. (cited by 299 papers: google scholar, June 2014)
[DRAM/Logic Integration]
Koji Inoue, Koji Kai, and Kazuaki Murakami, "Dynamically Variable Line-Size Cache Exploiting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIs,'' Proc. of The Fifth International Symposium on High-Performance Computer Architecture (HPCA-5), pp.218-222, Jan. 1999.
[DRAM/Logic Integration]
Koji Inoue, Tohru Ishihara, and Kazuaki Murakami, "High-Performance/Low-Power Cache Architectures for Merged DRAM/Logic LSIs (in Japanese), " IPSJ Journal, Vol. 42, No. 3, 419-431, May 2001. (40th Anniversary Best Paper Award)
Lovic Gauthier, Shinya Ueno, and Koji Inoue, "Hybrid Compile and Run-Time Memory Management for a 3D-Stacked Reconfigurable Accelerator," In Proceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES'13), Sep.-Oct. 2013. (acceptance rate: 21/68=31%)
[Performance prediction of Peta-Scale Supercomputers]
R. Susukita, H. Ando, M. Aoyagi, H. Honda, Y. Inadomi, K. Inoue, S. Ishizuki, Y. Kimura, H. Komatsu, M. Kurokawa, K. Murakami, H. Shibamura, S. Yamamura, Y. Yu, "Performance Prediction of Large-scale Parallel System and Application using Macro-level Simulation," International Conference for High Performance Computing, Networking, Storage and Analysis (SC08), Nov. 2008. (acceptance rate: 59/277=21.3%)